Hi, my name is Sidharth Padmanabhan.
I'm a Master's student in Informatics at Università della Svizzera italiana (USI), Lugano, Switzerland, currently working with Prof. Deborah Sulem.

I received my Bachelor's (B.Tech) in Electronics and Computer Engineering from Amrita Vishwa Vidyapeetham in 2025. My final year project was completed under the guidance of Prof. Ragesh Rajan. Throughout my studies, I worked closely with Prof. Poorna S S and Prof. Anuraj K. During my Bachelor's journey, I joined Prof. Rajesh Kannan Megalingam's HuT Labs as a Research Intern in 2023.

E-mail: sidharth [dot] padmanabhan [at] usi [dot] ch

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In order to attain the impossible, one must attempt the absurd
- Miguel de Cervantes

News

Sep 2025
Started MSc in Informatics at Università della Svizzera italiana (USI), Lugano 🇨🇭
Aug 2025
Book chapter on "Blockchain for 6G M2M Communication" published in IGI Global
Aug 2025
Graduated B.Tech in Electronics & Computer Engineering from Amrita Vishwa Vidyapeetham 🎓
Dec 2024
Paper on "Staircase Classification" published at ICONAT 2024
Nov 2024
Paper on "COVID-19 Detection from Cough Audio" published at ICCIDA 2024
Oct 2024
Book chapter on "Blockchain-IoT in Healthcare" published in IGI Global
Past updates
Feb 2024
Started Research Internship at SUTD, Singapore 🇸🇬
Aug 2023
Started Research Internship at HuT Labs

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Research & Work Experience

[Feb 2024 - Apr 2024] Research Intern - Robotics, Singapore University of Technology and Design (SUTD), Singapore
[Aug 2023 - Feb 2024] Research Intern - Machine Learning, HuT Labs, Kerala, India
[Oct 2022 - Jan 2023] Full Stack Developer, Teambi0s, Kerala, India

Activities

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